Honored Contributor
Honored Contributor--- quote start ---
<!--quotebegin-queisser@Feb 23 2006, 04:05 PM other than 0x5a, which other addresses fail?
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=12925)
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--- Quote End --- I made my own independant Verilog core to read the whole CFI Table, no NIOS processor or RAM or anything else... and it reads it flawlessly multiple times. This would indicate some sort of Signal-integrity error... when I add the nios processor, DDR etc.. that's when that byte starts to go weird. But no highs peed components are next to the Flash, so I don't understand why it would be an SI issue. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12926)</div> [/b] --- Quote End --- Spooky! Can you put a signal analyzer or scope on the physical pins themselves and look at the timing difference between the plain Verilog and NIOS system? Also, is it clock frequency dependent?
