own board, design considerations?

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originally posted by svhb@Jan 3 2006, 06:51 AM

you don't need the germs anymore since you can download across the jtag cable. this takes a processor that is a little bit bigger due to the jtag debug interface, but is much quicker to download.

you can also do the printf thing trough the jtag clable, but i prefer the uart approach here.

stefaan

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True. My guess is that the RAM required will cause the choice of a fairly powerful FPGA thus making it possible to waste a few hundred LEs for the bigger JTAG debugger designs.

BUT :-) with a multiple CPU design you will want each CPU&#39;s input and output under your control. This will imply using more than one JTAG port. The serial port uses less LEs and (with enough serial ports available on the PC, or using more than one PC) you can have a monitor window open for each one.

BTW, to get more serial ports on your PC have a look at the FDTI chip: FT2232. It is a USB to serial (dual) converter. I think it is about $10. You must just clamp the Rx pin on the FPGA as the output is 5V from the FT2232.

The designer has to tradeoff costs and ease of development. I personally would design a board with all external RAM and FLASH, get the code done quickly and then miniaturize it to infinitesimal.

This is infact what I have done so far. My project is now 50% complete. I did the initial design with small Cyclone I device, 128 kb SRAM, 1MB flash and support electronics. The final design will either be targeted for a 2C20 or 2C35 (depending on the final code size) and the appropriately sized EPCS chip.

VictorS