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originally posted by victors@Jan 3 2006, 01:45 PM
just remember to optimize your development path. if you skip the uart (or similar- even it is slow) development upload route then you will have very little feedback and you will have to recompile your fpga each time with the new srec files. by using something like the germs monitor you will lose 1k to 1.5k of precious ram but you can very quickly change/check something.
victors --- Quote End ---
You don't need the GERMS anymore since you can download across the JTAG cable. This takes a processor that is a little bit bigger due to the JTAG debug interface, but is much quicker to download.
You can also do the printf thing trough the JTAG clable, but I prefer the UART approach here.
Stefaan
Honored Contributor
