Omitting dcache AND icache in f-core

Hi Jackie,

the Avalon-bus can issue a transfer every cycle, however there is some latency (pipelining) for every transfer. This is necessary to achieve the fmax, I think. As soon as you have a branch, you get this latency penalty from the Avalon-bus (in addition to CPU-internal pipelining). I think this is the main reason for instruction cache. Pure speculation: As the instruction cache cannot be disabled, I suppose the nios2-core itself is no longer latency-aware as the nios1 was, only together with the i-cache.

But I understand your toughts, you could also think it in the other way with using all the available M4Ks as cache and store the complete programm in the cache. But this is not possible, I think. If you are using the EPCS or another external flash, a solution could be to build such a large cache and execute the code from the EPCS or external flash. This would be very slow until everything is in the cache, but after that there would never be cache misses because the cache is large enough.

BTW: Beside the Nios being generally pretty quick, there are some extra-cycles here and there that you would not have expected from the documentation. Especially loads from memory without data-cache are really slow. So if you really need performance, try to keep your things in the registers or use the data-cache. However, most of my observations were with the s-core. Without data-cache you may be better of with the s-core anyway.

Thomas