Omitting dcache AND icache in f-core

Thank you for your information BadOmen!

To sort things out, I completely agree with your explanation of the main purpose of caches. However, what happens when cache and memory operate at the same speed? In my design only on-chip memory - every M4k block not used by other entities - is present. As I understand the documentation of Avalon bus a read transfer may be issued in each cycle, no latency. So the complete transfer is finished within one cylce. I do not understand, why fetching from cache should be faster than that.

jackie