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Altera_Forum
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14 years ago

Offset in received SPI data

Hi, I am currently working on a project in which altera FPGA is the slave SPI. Transferred data is 21 words long. Each test packet looks like: 0x0001, 0x0002, 0x0003,...,0x0021, and it cou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

SPI master is repeatedly sending 1,2,..21 with pause between packets.

And the result is always the same.

The only unusual feature of the master is that SS is toggled on every word transmitted.

I tried to add IORD_ALTERA_AVALON_SPI_RXDATA(base) before every packet handling. In that case the 1st packet is OK (0x0001, 0x002, ...0x0021), but others are corrupted.