Object mode buffer VHDL

How do you use the buffer in VHDL, I get errors saying that I need to change object mode to buffer. Here is a piece of the code where it is telling me to use it.

This is not the whole code:

Thanks

Heath

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY mux4to7segdisplay IS

PORT ( NUM1 :IN std_logic_vector (3 DOWNTO 0);

NUM2 :IN std_logic_vector (3 DOWNTO 0);

S :IN BIT;

--bcd :IN std_logic_vector (3 DOWNTO 0);

A :OUT BIT;

B :OUT BIT;

C :OUT BIT;

D :OUT BIT;

E :OUT BIT;

F :OUT BIT;

G :OUT BIT);

END mux4to7segdisplay;

ARCHITECTURE display OF mux4to7segdisplay IS

BEGIN

PROCESS (S,NUM1,NUM2,A,B,C,D,E,F,G)

BEGIN

IF (S='0')Then

IF (NUM1="0000") THEN

A<='1';

B<='1';

C<='1';

D<='1';

E<='1';

F<='1';

G<='0';

ELSIF(NUM1="0001")THEN

A<='0';

B<='1';

C<='1';

D<='0';

E<='0';

F<='0';

G<='0';

ELSIF(NUM1="0010")THEN