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Altera_Forum's avatar
Altera_Forum
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15 years ago

non-cacheable instruction memory

Hi at all, I'm new in this forum. I create a Nios II system containing a Nios II/f core, with 2k data cache and 2k instruction cache, and 128k of on chip-memory. I want to run on this system an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Like DSL said you need to make sure a CPU data master is hooked up to the other port of the tightly coupled memory (dual port the memory first). You can use the Nios II data master or a tightly coupled data master for this purpose.