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Altera_Forum's avatar
Altera_Forum
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15 years ago

non-cacheable instruction memory

Hi at all, I'm new in this forum. I create a Nios II system containing a Nios II/f core, with 2k data cache and 2k instruction cache, and 128k of on chip-memory. I want to run on this system an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

How big is the memory area - looks like you need at least 32kb.

Did you give the cpu data access to the instruction memory (via the Avalon bus and it's second port) that access is needed to allow the JTAG to download code, it is also needed if there is any data (eg .rodata or switch statement jump tables (esp. gcc4)) in the code.