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Altera_Forum
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15 years ago

non-cacheable instruction memory

Hi at all, I'm new in this forum. I create a Nios II system containing a Nios II/f core, with 2k data cache and 2k instruction cache, and 128k of on chip-memory. I want to run on this system an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you, I must implement a test for instruction cache, for this reason I must jump from the cacheable section of the assembly program to the non cacheable one. My problem is to know the instruction useful to inform the linker using a assembly code.

My first problem is error given during the NiosII Application and BSP from Template.

In this application I include a .sopciifo file relative to a system like the one in attach.

During the creation of the application I receive this error:

Failed to execute: ./create-this-bsp --cpu-name cpu_0 --no-make

SEVERE: nios2-bsp-create-settings failed.

SEVERE: Tcl script "bsp-set-defaults.tcl " failed: Section ".rodata" has no memory region mapping.

nios2-bsp: nios2-bsp-create-settings failed

:confused::confused::confused:

What does it means?????