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Altera_Forum
Honored Contributor
Honored Contributornon-cacheable instruction memory
Hi at all, I'm new in this forum. I create a Nios II system containing a Nios II/f core, with 2k data cache and 2k instruction cache, and 128k of on chip-memory. I want to run on this system an ...
Altera_ForumHonored Contributor
Honored ContributorYou can't, instructions read from an Avalon slave have to read into the instruction cache first.
What you can do is use a tightly coupled memory block for the instructions. You'll probably need to make the memory blocks second port a slave to the avalon bus and give the cpu data access to it. If you want to use the jtag debugger, you'll still need the instruction master and a minimal instruction cache.
