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Julien's avatar
Julien
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

NIOSII/e peripheral IO read access performance?

Hi, I am using a design that includes a NIOSII/e (the "e" is important here), that accesses a UART IP as an Avalon slave. Works fine, but I timed the duration of each individual word read access, an...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Julien,

  1. Instead of using UART IP(Because IP is like UART or SPI are slow) use on chip ram to see the difference in timing also use Alavon Pipeline IP.
  2. Use signal-tap and monitor the av_ld_waiting_data or av_ld_waiting_data_nxt signal. you can find that time given in document matches the processor time excluding the time on waiting for response or request.

Attached image of signal-tap image hope it helps.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand