Forum Discussion
Julien
Occasional Contributor
Occasional ContributorNIOSII/e peripheral IO read access performance?
Hi, I am using a design that includes a NIOSII/e (the "e" is important here), that accesses a UART IP as an Avalon slave. Works fine, but I timed the duration of each individual word read access, an...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi,
Yes, you are correct.but Duration of Avalon-MM read transfer is variable right,
Avalon-MM transfers transmit up to 1024 bits at a time, and take one or more clock cycles to complete(The shortest duration of an Avalon-MM transfer is one cycle).
One instruction per 6 clock cycles so 6 cycle is the max, No processor executes a full command in one single clock cycle.
However try optimizing the design that may help to reduce the timing.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand
