NiosII with Altera SDRAM controller performance

I agree with Michel's opinion.

Burst adapters inserted by Qsys is over-design from Avalon interconnect perspective and may reduce system Fmax. Right now the most efficient bursting is to ensure that both Master-Slave share the same burst properties, such as line or wrap burst and burst sizes. Nios itself supports fixed burst of 8 at both instruction and data masters but they employed wrapping and incremental burst types respectively. This makes it complicated to create a slave interface with burst that fits both cases.

I think the value of 8 is used because Nios perform pipeline reads at size fixed at 8 as this is supported cache line size (D-cache can be configured for 4,16,32(default) bytes, I-cache fixed at 32 bytes). Let's say you have other masters connected to the SDRAM, 8 may not be the optimum value. In essence, "arbitration share" controls the interconnect behavior and is system dependent. For equality purpose, Qsys always defaulted to '1' for equal arbitration distribution and does not make any assumptions that user needs weighted distribution such as in Nios-SDRAM case.

Overall, that is good findings though. Should recommend to Altera FAEs.