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Altera_Forum
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19 years ago

NiosII Uart Interrupt Handler

Hi!! I wrote Uart Interrupt Handler For NiosII. and use it. [CODE] //----------------------------------------------------------------------------- //Description : Uart Interrupt Handler & Q Buffe...
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Altera_Forum
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10 years ago

Dear want2know,

Regarding you 4th query, Interrupt for UART (or any other IP core) is required to be registered only once, and repeating any such lines like "alt_ic_isr_register(uart1_irq_interrupt_controller _id, uart1_irq,isruart1,&context_uart,0x0);" will not make any difference, its only the number of times the interrupt comes that matters. Like in the code of bluegem he has enabled only the interrupt for RXDATA register, by writing to the CONTROL register of the UART, read the Altera Peripherals IP guide for details regarding the UART IP core.

Regarding 5th query, In IsrUart1(), bluegem is receiving the data, and writing to rx_buffer_1 most of the times, because the interrupt for Data Reception is permanently enabled and he enables the interrupt generation for Transmission, only when the UART is still not ready to accept new data for Transmission. This thing he is doing in PutUart1() function, and he is writing the data to tx_buffer_1 when the UART is not ready for Immediate Transmission of data. Hence whenever the next Interrupt from UART arrives (but now since both the Interrupts, i.e. for Transmission & Reception are enabled, hence Interrupt can happen because of both reasons), lets assume that this time interrupt arrives for Transmission, hence the data to be Transmitted is written in TXDATA register for Transmission.

Regarding your query for below

"in the function putuart1(), if (++txhead_1 > (tx_buffer_size_1-1)) txhead_1 = 0;

z = iord_altera_avalon_uart_control(uart1_base) | altera_avalon_uart_control_trdy_msk;

iowr_altera_avalon_uart_control(uart1_base, z);

i am wondering what is the purpose of having the codes checking the buffer size and the head and tail? txhead_1==txtail_1"

TxHead just points to data which is to be transmitted and TxTail points to the Data which has been Transmitted and the difference between them gives the pending data which is yet to be transmitted. In the above case, bluegem is first checking whether UART is ready for accepting a new data for transmission, if it is ready then the condition txhead_1==txtail_1 will hold true, otherwise the data will be written in tx_buffer_1 and TxHead_1 will be incremented, this is further followed by enabling of Interrupt generation for Transmission, this he is doing in following code-segment "z = iord_altera_avalon_uart_control(uart1_base) | altera_avalon_uart_control_trdy_msk;iowr_altera_avalon_uart_control(uart1_base, z);". And whenever the next Interrupt from UART arrives the data pointed by TxTail_1 is written in the TXDATA register of UART for Transmission.

I think I have tried for clarifying your queries, any more update on the same please tell me or correct me if I am wrong