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Altera_Forum
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15 years ago

NiosII is slow? Or something I am doing wrong.

Hi all, I am playing with Cyclone II chip. It is custom board and there is ATMEGA16 running at 12MHz and FPGA with master clock 50MHz. FPGA is translating data from internal dualport memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The hand optimized libm.a is part of the winavr package. How big was your compiled AVR code? Using libm.a my result was about 1.5k. Without libm.a the size was almost 4k.

I did compile Nios with hardware floating point, the code was just under 2k.

I don't think the main problem is the C compiler, but more the C library and lack of hardware for more FP operations. The default floating point implementations provided in the C library are not very efficient and not optimized for Nios. Even with hardware floating point turned on, this only accelerates the basic math functions (+, -, *, /), not things such as comparisons or conversions to or from integers.

I did come across this alternate custom floating point unit (http://www.nioswiki.com/custom_floating_point_unit). I suspect it could make a big difference for your test program.

I am kinda surprised that the Altera FP unit does not include acceleration for more FP operations.

Of course, if you really want to see the FPGA shine, you should create application specific acceleration. I stumbled across a site about an fpga based mandelbrot generator (http://markbowers.org/home/fpga-mandelbrot) you may find interesting.