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I would expect this algorithm to be slow. This algorithm is performing many floating point calculations and without the floating point custom instruction all of that would end up being emulated in software using Nios II. The algorithm is also inherently slow as are most convergence algorithms and as a result you can speed it up by breaking down the algorithm and handling it in parallel (multi-core or hardware accelerators).
Why the performance is different between the two cores I'm not sure but make sure you are using the same compiler optimizations so that you are comparing apples to apples.
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Maybe you didn't understand main post. English is not native language for me. I want to emphasize, that ATMEGA16
do not have any FP instruction at all. NiosII in this experiment
has hardware multiplication, addition and substraction (software emultation didn't fit to this fpga). Nios is 32 bits wide (how many bits floats have?) and Mega is only 8 bit. And clock speed of Nios is
4 times! faster.
I do not modify algorithms as it is fair play- same code is copy-pasted from one platform to other.
And the question "Why the performance is different between the two cores" is answered in very simple way. Who will pay money for "f" version if "e" version is same. :)
Honored Contributor
