NIOSII addressing for 32 bit wide SDRAM

Ok, I started an SR with Altera and they said:

>>When NIOS II (32 bit Master) is trying to access your memory controller (64 bit slave), >>Master Byte Address will need to be at incremental of 8.

>>Could you please refer to Avalon Interface specification document for better

>>explaination. http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

>>Table 3-3

>>Such incremental step is required for Avalon bus interfacing between NIOS-II and your

>>memory controller local bus, and it is not related with memory burst length setting

>>(x4 or x8) in memory controller.

So, this confirms my suspicion and experiments that the address needs to increment by 8.

But note you still only get 4 bytes of data per address increment of 8.

In the same SR update I had asked two other questions which did not get answers

(common with Altera SR feedback depending on the support individual):

1) ie. how do I access ____ALL____ 256MB of this device.

2) Does this mean we ____WILL____ only see half of our memory???

So, the span generated is 0x10000000 for 256MB DDR and I thus cannot access past

this span and thus with address increments of 8 I will only see half the memory

and would need a span twice this size to see it all. No? Else how do I see all the mem.

Thoughts?

Regards.