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Altera_Forum's avatar
Altera_Forum
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14 years ago

nios2 processor non responsive

Hello everyone.

I have created a design in SOPC builder with a NIOSIIf core which has a MMU. The SOPC file for the same is here (https://docs.google.com/open?id=0b8b-p7uizx09ztfmnwi0ntqtmdcyni00mty5ltlkotutmwnkyjq5zgi1m2mw).

Furthermore, I am using a DE1 board so I have used the pin assignments that came with the CD. I instantiate the core in a BDF file and then attach pins to it. The entire project contents can be found here (https://docs.google.com/open?id=0b8b-p7uizx09otu2njewyzatndflny00mdg0lthlzjctmzrkodyyngm3mjc0). The quartus version is 11.1sp1.

After I instantiate I burn the design using nios2-configure-sof and then later I try to download the image of uboot which I created as described in the wiki (http://www.alterawiki.com/wiki/dasuboot). On issuing the following command:

nios2-download -g u-boot

I get the following errors:

Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused

On searching the net, the most I could get was that the reset pin gets asserted and hence the processor is never able to get out of reset. But in my own case, I have connect the reset_n input pin to KEY[0] the first pushbutton switch which when pressed connects the pin to ground.

Some people were also told to try the design using an e core instead of an f core here (http://www.alteraforum.com/forum/showthread.php?t=32665&highlight=nios2+processor+non+responsive). By the way, is the DE1's 8MB of SDRAM that insufficient even for downloading the u-boot image? Which is hardly 530 KB. Then again it is not even getting downloaded in the first place

Some people said that it is time limited for the f version...which even my sof tells me..but this happened the very first time and then it never changed..

Some fellows were trying to use C++ libraries while creating a BSP. Where should I start looking?? Itd be great to hear some tips, pointers from people here.

Regards,

Aijaz

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi daixiwen..

    thanks for the advice..adding the avalon MM pipelined bridge seems to work. Atleast I do not see any timing violations in my design in Linux..

    Additionally I do not understand what you mean by

    --- Quote Start ---

    Oh and just to be sure... you do know that if you have the Opencore evaluation window open after having configured the FPGA, you de need to keep it open, don't you? If you close it then the Nios CPU will stop.

    --- Quote End ---

    What exactly is this window here? And do I need to close it before downloading the SOF?? or otherwise always keep it open as long as I want my nios2 to work??

    Thanks in advance :)
  • Altera_Forum's avatar
    Altera_Forum
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    It is a window that is opened if the Quartus programmer uploaded a time limited .sof (which happens when you compiled a design with cores you don't have the license for). It says something like "opencore plus evaluation" and prevents you from using the programmer further. You need to keep this window open, or else all the licensed components (including the Nios II CPU) cease to work.