NIOS2 & mSGDMA (Ethernet example)

lostdestiny,

thank you for your help

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The descriptor_slave should connect to the .data and .instruction Master of your NIOS processor. To my understanding, this is where the descriptors are written to when you call construct_standard_mm_to_mm_descriptor(). The Data_read_master connects to your memory where the source data resides, and the write data master should connect to the memory where you want the source data to be written.

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my system consists of a NIOS2, on OnChipMemory (OCM) which acts as the RAM pool for the NIOS system, I would like the DMA controller to send data to this memory, so indeed I connected the master interface of the DMA controller to the Pipeline bridge. The descriptor slave interface of the DMA controller was connected to the Master interface of the CPU bridge, as I thought it would directly receive instructions from the CPU.

I did not connect the CPU/instruction master interface to the DMA controller (as you mentionned it), I tried to do so, but I keep getting "CPU/instruction master is read only while the CPU/instruction master is write only" which I don't understand, it's not connected to itself, I already have devices on the instruction master line, I am just trying to add a new one.

Here's what I tried:

• DMA-Controller
• DMA-Controller
• DMA-Controller
• cant connect descriptor slave to instruction master because of previous error

• cant connect descriptor slave to a master interface without connecting

Here's my code:

alt_u32 dma_buf; // work buffer / OCM??
alt_msgdma_dev *dma_dev;
alt_msgdma_standard_descriptor rx_descriptor;
// tried with & without it --> alt_msgdma_standard_descriptor rx_descriptor ___attibute__ ((section(".onchip_memory"));
// copied from available example, I doubt we need this though because
// the API sets the destination address when we build the descriptor right?
main(){
  
  dma_dev = alt_msgdma_open("/dev/msgdma_csr");
  alt_msgdma_construct_standard_st_to_mm_descriptor(
     dma_dev,
     &rx_descriptor,
     (alt_u32*)dma_buf,
     256*sizeof(int),
     0
   );
   dma_status();
   alt_msgdma_standard_descriptor_async_transfer(dma_dev, &rx_descriptor);
   dma_status();
}

my dma_status() routine checks the CSR status reg, the first one (right after build_descriptor()) says "RESET state + descriptor buffer EMPTY".

The second one, right after _async_transfer() says "descriptor buffer EMPTY", which lets me think there is some activity but I am not able to control my DMA descriptors properly.

I haven't tried direct register access yet, like setting the GO bit & manually controlling the descriptors, I think I should be able to get the API to work.

Is an OCM dedicated to DMA descriptors mandatory?

Is CPU/Instruction master connection mandatory?

How can I connect an OCM/FIFO to store DMA descriptors to the DMA controller with connecting the [mm_write] interface??