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Honored Contributor
Honored Contributornios with custom fpga logic
Hello everybody. I am trying to set up a simple example where I implement a simple XOR gate in fpga logic. Then in C code written for the NIOS processor, I will pass several numbers to be XOR'd, an...
Altera_ForumHonored Contributor
Honored ContributorWhat is the read latency of your slave interface avalon interface? Seems like your hdl avm_read has latency of 1 cycle. Must set it accordingly in the qsys component.
