Nios system without jtag communication

The jtag communication port is generally used as a debug port. It allows communication to NIOS via the same port where you personalize the FPGA and download your firmware. This configuration, however, is volatile, and is lost during a power cycle. For a stand alone application, you will need to provide a flash device that the FPGA will read upon power-up. The flash would also contain your firmware. No PC communication would be required. Altera has utilities that allow you to program the flash via a Byte or USB blaster, so it is a bit confusing when first starting out.