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Altera_Forum
Honored Contributor
Honored ContributorNIOS SDRAM performance
I have measured the speed of memcpy's of NIOS2. I use optimized code consisting of four consecutive READs and four consecutive write accesses. Code snippet: while (i--) {
d0 = __built...
Altera_ForumHonored Contributor
Honored ContributorHello Jesse,
the main reason why we (me and my colleagues) have chosen a FPGA based solution is that we needed some custom peripherals that can share memory with a CPU http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif . Additionally, small portions of the shared data has to be copied around in memory, that's what I need memcpy performance for. And, my total shared mem is ~2MB in size, so on-chip RAM won't do http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif Technically, where do these 12 cycles come from? I'd expect to see 2 or 3 cycles between reads, not 12. But I see your argument (size/speed tradeoff), this is reasonable. For my application, I'd like a wizard option to choose between a small or fast data master, just as for the NIOS2 core. Dirk
