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Altera_Forum
Honored Contributor
10 years agoHi
mikedsouze and ted thanks for your time, I think i have not conveyed properly. The memory value is updated at every 48 MHz, after updating the all 512 locations and time elapsed is 640usec (if these 2 conditions are met) FPGA (Stratix V) will give PIO Trigger. Now at NIOS-II side ISR is implemented to read the all 512 locations. What i feel is time available to read the contents is worst case 640usec. As NIOS-II is running at 200MHz i should not miss any data. How i am checking data is missed, out of 512 locations one location is sequence number. Out of 100 times i do this operation one or 2 times i am missing data.I am simply copying the present data and comparing the sequence number of the previous buffer data, ideally it should be always one. But sometimes value is other than one, this is happening once in hundred times. Regards, Siva