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Altera_Forum
Honored Contributor
9 years agoNios Read Data Never Appears on Nios Read Bus
In our Arria 10 design, we have a custom IP block for the Nios data and instruction memory. The underlying memory consists of two 4Kx32 memory blocks, shared with other 64-bit processing elements in...
Altera_Forum
Honored Contributor
9 years agoJust glancing but having been in your shoes,
uav_readdatavalid is a qualifier for uav_readdata[], so your tag for event (8) should actually be one line above event (9), in which case you'll see they aren't in sync. Your data 00000001h shows up one clock later. With a fixed latency slave, you can tweak the "readLatency" attribute in your _hw.tcl to get them to align. You mentioned inserting wait states, but you didn't include the waitrequest signal in your trace? You probably want your trace to look more like Figure 3-5 from mnl_avalon_spec.pdf, but right now you're looking more like Figure 3-6.