Nios problem with interfacing custom component

I would try to use the write signal instead of byteenable to qualify the writedata into the light_avalon module.

module light_avalon(clock, resetn, D, write, Q);

input clock, resetn;

input write;

input [15:0] D;

output reg [7:0] Q;

always @(posedge clock)

begin

if (write) Q[7:0] <= D[7:0];

end

endmodule

The reason is that the Avalon interface into the light_avalon_interface can be receiving writedata, which is not intended for the light_avalon. By using the write signal, you will guarantee that the writedata is valid for your module.

Hope this helps.