New Contributor
Occasional ContributorHi gdoralsa,
HPS and/or NIOSV hardware development is done in Platform designer. With an HPS+(LP)DDR4 established system, you can add to it the NIOS-V and connect its instruction_manager and data_manager busses to the HPS fpga2hps pipe.
The NIOS-V needs an onchip_memory at its base address of 0x0000_0000 for its code execution. The NIOS-V Reset Vector needs to be set to this SRAM, or Absolute address 0x0000_0000.
Does this help?
New ContributorThe NIOS design is done by a different vendor. They provide a design-partitioned “.QXP” file either as a post-synthesis or post-fitting type. That design file can only be imported and used by the project that has the HPS-based design. Both designs are done with the same FPGA device part number. So one design can be imported to the other. However, source files from the design partition not available.
Both exchange data but operate independently. Both will have their own memory map.
Doing it all in one platform designer (add NIOS) and doing FPGA2HPS is not how we can do it because NIOS-based source files are not available.
Super ContributorYou'll need to export the HPS bridges out of PD and connect them in code.
