NIOS inb does 4 byte accesses to UART

I seem to have isolated the cause, but I don't fully understand the reason. The UART SOPC Builder module was originally setup for Dynamic (Memory) mode for another project which needed the UART registers to take up only 8 bytes. In this mode single byte NIOS reads get translated into 4 byte reads of the corresponding LWord. Reading a single byte from an external (to the FPGA) Master works just fine.

I created a new SOPC Component with Native (Register) mode which then increased the UART register space to 32 bytes. I changed the register shift to 2 in the serial.h file and this corrects the problem and the UARTS work fine. I only see a single byte accesses to the UART as expected.

I still don't understand why reading a single byte from a Dynamic Memory from the NIOS processor gets translated into reading all 4 bytes of the corresponding LWord. It appears that the NIOS treats Dynamic and Native address spaces differently.

It's annoying to have two nearly identical components, but I guess that's what I am stuck with.

Stefan