Hi,

I made a custom Nios II system on a DE2 board, using SOPC Builder. I had much trouble putting it to work (due to PLL issues), but finally made it with the help of this forum.

After it worked, I tried to upload a uClinux image to the board. But it is hanging and I have no clue of what is going wrong this time.

I searched the forum and found nothing on this problem.

Here's my header file:

#define CPU_IMPLEMENTATION "fast"# define BIG_ENDIAN 0# define CPU_FREQ 100000000# define ICACHE_LINE_SIZE 32# define ICACHE_LINE_SIZE_LOG2 5# define ICACHE_SIZE 4096# define DCACHE_LINE_SIZE 4# define DCACHE_LINE_SIZE_LOG2 2# define DCACHE_SIZE 4096# define FLUSHDA_SUPPORTED # define HAS_JMPI_INSTRUCTION # define MMU_PRESENT # define KERNEL_REGION_BASE 0xc0000000# define IO_REGION_BASE 0xe0000000# define KERNEL_MMU_REGION_BASE 0x80000000# define USER_REGION_BASE 0x0# define PROCESS_ID_NUM_BITS 8# define TLB_NUM_WAYS 16# define TLB_NUM_WAYS_LOG2 4# define TLB_PTR_SZ 7# define TLB_NUM_ENTRIES 128# define FAST_TLB_MISS_EXCEPTION_ADDR 0xc0000000# define EXCEPTION_ADDR 0xc0100020# define RESET_ADDR 0xc0100000# define BREAK_ADDR 0xc0001020# define HAS_DEBUG_STUB # define HAS_DEBUG_CORE 1# define HAS_ILLEGAL_INSTRUCTION_EXCEPTION # define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION # define HAS_EXTRA_EXCEPTION_INFO # define CPU_ID_SIZE 1# define CPU_ID_VALUE 0x0# define HARDWARE_DIVIDE_PRESENT 0# define HARDWARE_MULTIPLY_PRESENT 1# define HARDWARE_MULX_PRESENT 0# define INST_ADDR_WIDTH 29# define DATA_ADDR_WIDTH 29# define NUM_OF_SHADOW_REG_SETS 0 /* * Macros for device 'onchip_memory', class 'altera_avalon_onchip_memory2' * The macros are prefixed with 'ONCHIP_MEMORY_'. * The prefix is the slave descriptor. */# define ONCHIP_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2# define ONCHIP_MEMORY_COMPONENT_NAME onchip_memory# define ONCHIP_MEMORY_BASE 0x0# define ONCHIP_MEMORY_SPAN 1024# define ONCHIP_MEMORY_END 0x3ff# define ONCHIP_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0# define ONCHIP_MEMORY_INIT_CONTENTS_FILE "onchip_memory"# define ONCHIP_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0# define ONCHIP_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"# define ONCHIP_MEMORY_WRITABLE 1# define ONCHIP_MEMORY_DUAL_PORT 1# define ONCHIP_MEMORY_SIZE_VALUE 1024# define ONCHIP_MEMORY_SIZE_MULTIPLE 1# define ONCHIP_MEMORY_CONTENTS_INFO ""# define ONCHIP_MEMORY_RAM_BLOCK_TYPE "Auto"# define ONCHIP_MEMORY_INIT_MEM_CONTENT 1# define ONCHIP_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0# define ONCHIP_MEMORY_INSTANCE_ID "NONE"# define ONCHIP_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"# define ONCHIP_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32# define ONCHIP_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0# define ONCHIP_MEMORY_MEMORY_INFO_GENERATE_HEX 1# define ONCHIP_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR# define ONCHIP_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1# define ONCHIP_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR /* * Macros for device 'timer', class 'altera_avalon_timer' * The macros are prefixed with 'TIMER_'. * The prefix is the slave descriptor. */# define TIMER_COMPONENT_TYPE altera_avalon_timer# define TIMER_COMPONENT_NAME timer# define TIMER_BASE 0x400# define TIMER_SPAN 32# define TIMER_END 0x41f# define TIMER_IRQ 1# define TIMER_ALWAYS_RUN 0# define TIMER_FIXED_PERIOD 0# define TIMER_SNAPSHOT 1# define TIMER_PERIOD 1# define TIMER_PERIOD_UNITS "ms"# define TIMER_RESET_OUTPUT 0# define TIMER_TIMEOUT_PULSE_OUTPUT 0# define TIMER_FREQ 100000000# define TIMER_LOAD_VALUE 99999ULL# define TIMER_COUNTER_SIZE 32# define TIMER_MULT 0.0010# define TIMER_TICKS_PER_SEC 1000 /* * Macros for device 'leds', class 'altera_avalon_pio' * The macros are prefixed with 'LEDS_'. * The prefix is the slave descriptor. */# define LEDS_COMPONENT_TYPE altera_avalon_pio# define LEDS_COMPONENT_NAME leds# define LEDS_BASE 0x420# define LEDS_SPAN 16# define LEDS_END 0x42f# define LEDS_DO_TEST_BENCH_WIRING 0# define LEDS_DRIVEN_SIM_VALUE 0x0# define LEDS_HAS_TRI 0# define LEDS_HAS_OUT 1# define LEDS_HAS_IN 0# define LEDS_CAPTURE 0# define LEDS_BIT_CLEARING_EDGE_REGISTER 0# define LEDS_BIT_MODIFYING_OUTPUT_REGISTER 0# define LEDS_DATA_WIDTH 8# define LEDS_RESET_VALUE 0x0# define LEDS_EDGE_TYPE "NONE"# define LEDS_IRQ_TYPE "NONE"# define LEDS_FREQ 100000000 /* * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart' * The macros are prefixed with 'JTAG_UART_'. * The prefix is the slave descriptor. */# define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart# define JTAG_UART_COMPONENT_NAME jtag_uart# define JTAG_UART_BASE 0x430# define JTAG_UART_SPAN 8# define JTAG_UART_END 0x437# define JTAG_UART_IRQ 2# define JTAG_UART_WRITE_DEPTH 64# define JTAG_UART_READ_DEPTH 64# define JTAG_UART_WRITE_THRESHOLD 8# define JTAG_UART_READ_THRESHOLD 8 /* * Macros for device 'serial', class 'altera_avalon_uart' * The macros are prefixed with 'SERIAL_'. * The prefix is the slave descriptor. */# define SERIAL_COMPONENT_TYPE altera_avalon_uart# define SERIAL_COMPONENT_NAME serial# define SERIAL_BASE 0x440# define SERIAL_SPAN 32# define SERIAL_END 0x45f# define SERIAL_IRQ 3# define SERIAL_BAUD 115200# define SERIAL_DATA_BITS 8# define SERIAL_FIXED_BAUD 1# define SERIAL_PARITY 'N'# define SERIAL_STOP_BITS 1# define SERIAL_SYNC_REG_DEPTH 2# define SERIAL_USE_CTS_RTS 0# define SERIAL_USE_EOP_REGISTER 0# define SERIAL_SIM_TRUE_BAUD 0# define SERIAL_SIM_CHAR_STREAM ""# define SERIAL_FREQ 100000000 /* * Macros for device 'sram', class 'altera_up_avalon_sram' * The macros are prefixed with 'SRAM_'. * The prefix is the slave descriptor. */# define SRAM_COMPONENT_TYPE altera_up_avalon_sram# define SRAM_COMPONENT_NAME sram# define SRAM_BASE 0x100000# define SRAM_SPAN 524288# define SRAM_END 0x17ffff /* * Macros for device 'flash', class 'altera_avalon_cfi_flash' * The macros are prefixed with 'FLASH_'. * The prefix is the slave descriptor. */# define FLASH_COMPONENT_TYPE altera_avalon_cfi_flash# define FLASH_COMPONENT_NAME flash# define FLASH_BASE 0x400000# define FLASH_SPAN 4194304# define FLASH_END 0x7fffff# define FLASH_SETUP_VALUE 10# define FLASH_WAIT_VALUE 70# define FLASH_HOLD_VALUE 10# define FLASH_TIMING_UNITS "ns"# define FLASH_SIZE 4194304# define FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8# define FLASH_MEMORY_INFO_HAS_BYTE_LANE 0# define FLASH_MEMORY_INFO_IS_FLASH 1# define FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1# define FLASH_MEMORY_INFO_GENERATE_FLASH 1# define FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR# define FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR /* * Macros for device 'sdram', class 'altera_avalon_new_sdram_controller' * The macros are prefixed with 'SDRAM_'. * The prefix is the slave descriptor. */# define SDRAM_COMPONENT_TYPE altera_avalon_new_sdram_controller# define SDRAM_COMPONENT_NAME sdram# define SDRAM_BASE 0x10000000# define SDRAM_SPAN 8388608# define SDRAM_END 0x107fffff# define SDRAM_REGISTER_DATA_IN 1# define SDRAM_SIM_MODEL_BASE 0# define SDRAM_SDRAM_DATA_WIDTH 16# define SDRAM_SDRAM_ADDR_WIDTH 22# define SDRAM_SDRAM_ROW_WIDTH 12# define SDRAM_SDRAM_COL_WIDTH 8# define SDRAM_SDRAM_NUM_CHIPSELECTS 1# define SDRAM_SDRAM_NUM_BANKS 4# define SDRAM_REFRESH_PERIOD 15.625# define SDRAM_POWERUP_DELAY 100.0# define SDRAM_CAS_LATENCY 3# define SDRAM_T_RFC 70.0# define SDRAM_T_RP 20.0# define SDRAM_T_MRD 3# define SDRAM_T_RCD 20.0# define SDRAM_T_AC 5.5# define SDRAM_T_WR 14.0# define SDRAM_INIT_REFRESH_COMMANDS 2# define SDRAM_INIT_NOP_DELAY 0.0# define SDRAM_SHARED_DATA 0# define SDRAM_STARVATION_INDICATOR 0# define SDRAM_TRISTATE_BRIDGE_SLAVE ""# define SDRAM_IS_INITIALIZED 1# define SDRAM_SDRAM_BANK_WIDTH 2# define SDRAM_CONTENTS_INFO ""# define SDRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 16# define SDRAM_MEMORY_INFO_GENERATE_DAT_SYM 1# define SDRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIRAnd here's the output message:

brunosmartins@ubuntu:~/nios2-linux/uClinux-dist/images$ nios2-download -g zImage.initramfs.gz Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 1536KB in 30.1s (51.0KB/s) Verified OK Starting processor at address 0xD0500000

brunosmartins@ubuntu:~/nios2-linux/uClinux-dist/images$ nios2-terminalnios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster ", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) Uncompressing Linux... Ok, booting the kernel. Linux version 2.6.34-00692-g5bc7853-dirty (brunosmartins@ubuntu) (gcc version 4.1.2)# 24 Fri Jan 21 21:16:32 BRST 2011 bootconsole enabled early_console initialized at 0xe0000430 Linux/Nios II-MMU init_bootmem_node(?,0x1026b, 0x10000, 0x10800) free_bootmem(0x1026b000, 0x595000) reserve_bootmem(0x1026b000, 0x100) Built 1 zonelists in Zone order, mobility grouping off. Total pages: 2032 Kernel command line: PID hash table entries: 32 (order: -5, 128 bytes) Dentry cache hash table entries: 1024 (order: 0, 4096 bytes) Inode-cache hash table entries: 1024 (order: 0, 4096 bytes) We have 67584 pages of RAM Memory available: 5628k/2472k RAM, 0k/0k ROM (1251k kernel code, 1221k data) Hierarchical RCU implementation. NR_IRQS:32 Calibrating delay loop... And then, nothing more. Does "Calibrating delay loop" has to do with PLL timing/delay?

Thanks in advance

Bruno

Forum Discussion

Nios II with MMU hanging after boot

NIOS II "Verify failed" for on-chip memory 128k

Test Post

Error generating BSP

NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)

Where is FreeRTOS-Plus-TCP Design