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Altera_Forum's avatar
Altera_Forum
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20 years ago

NIOS II vs. NIOS I real (!) performance

Using NIOS-I as a controller with some percentage of signal processing tasks, we came across the fact that the CPU core uses 2 extra cycles for write access to on-chip RAM, 1 cycle for read access. This is more memory access penalty than for most controllers.

Cache does not have an influence. Moreover, cache is critical for our app due to its lack of determinism.

Question: Does anybody know if NIOS-II has faster access to on-chip memory? At least for the 2-cycle write delay, there does not seem to be an obvious reason in neither the Avalon spec nor the M4K interface.

Thanks!

Rolf

For those who are still interested in NIOS-I: I posted a more detailed analysis of do's and don'ts on our web at http://www.rpc-engineering.de/bin/view/kno...whow/nioscycles (http://www.rpc-engineering.de/bin/view/knowhow/nioscycles).

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I have good news! The next version of Nios II (version 5.0) has dramatically better read/write performance.

    This version should be available in a few weeks.

    I'm not at liberty to divulge complete details at this point since Nios II 5.0 hasn't been officially released.

    However, I can tell you that the read and write access times have been reduced in the Nios II/f by one cycle each if you use the new D-cache

    or if you remove the D-cache completely. This basically matches the Nios II/s read/write performance.

    There is also a new feature for the Nios II/f which reduces the access time for on-chip memory to values faster than Nios I.

    To be continued ...