Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

NIOS II Timer Interval Core Question!

Hi, I am trying to generate three different clock cycles; Given below is what i am trying to generate Clock1 ¯¯¯¯|_|¯|_|¯|_|¯|_|¯¯¯¯¯¯¯¯¯¯¯ Please note that clock 1 starts out high an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Could you shift register (or similar) to control each output once the main timer has expired?

I'm not sure what you mean by 'in sync' - you have multiple edges at the same time - they will not happen together!