NIOS II SPI Slave Issue

I have fixed the issue, the documentation from Intel is incorrect in the Embedded Peripherals IP User Guide page 50+ for MAX 10 Nios II.

https://cdrdv2.intel.com/v1/dl/getContent/732789?fileName=ug_embedded_ip-683130-732789.pdf

I simulated the IP in ModelSim and looking at the generated Verilog code there are some comments.

In the Embedded Peripherals IP User Guide it states that the core supports all 4 SPI modes. However in slave mode clock on raising edge is not supported. In master mode all 4 modes are supported.

*Limitation: Only support CPHA=1.

Changing the SPI mode to clock data on falling edge it works fine and without issue, the default configuration in the IP from Platform Designer is to clock on raising edge.

@EBERLAZARE_I_Intel

I have spent a while trying to solve this issue and the documentation should be updated. The documentation mainly covers master mode. Slave only support SPI modes 1 and 3. Also you must enable synchronisers.

sample from /submodules/spiphyslave.v

/************************************************************************** ^M
*Module name: MOSIctl ^M
*Date Created: 15 Nov 2007 ^M
*Last Modified: 15 Nov 2007 ^M
*Description: Transport Bytes downstream from SPI MOSI to avalon ST ^M
*             The SPI Master side consists of:  ^M
              1)  MOSI,nSS,Sclk ^M
*             ST side consists of: ^M
*             2) An Avalon ST source port (ready, valid, data) ^M
*              ^M
*Clock crossing: Clock crossing done using synchronizer and handshaking logic ^M
* ^M
*Limitation: Only support CPHA=1. ^M
* ^M
* MSB/LSB first: MSB first ^M
* ^M
* ^M
*Parameter: BITS_PER_SYMBOL,  ^M
*           SYMBOL_PER_BEAT,  ^M
*           CPOL (Clock Polarity) ^M
*           CPHA (Clock Phase) ^M
* ^M
*Global Define:  ^M
*Internal Parameter:  ^M
* ^M
*CPOL and CPHA description: ^M
* ^M
* CPHA=0: First edge of Sclk is used to capture data, sent at second edge of Sclk ^M
*         This means that first (LSB) byte must be send out from MISO when nSS is low ^M
* CPHA=1: First edge of Sclk is used to send data, second edge of clock capture data ^M
*         (CPHA=1 is used when we need the first edge of Sclk before sending data) ^M
* ^M
* ^M
* Below are data shifting and capturing timing for the 4 different mode for SPI ^M
* ^M
*    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^M
*    | SPI Mode | CPOL | CPHA | Shift Sclk edge   | Capture Sclk edge | ^M
*    | 0        | 0    | 0    | Falling (negedge) | Rising (posedge)  | ^M
*    | 1        | 0    | 1    | Rising (posedge)  | Falling (negedge) | ^M
*    | 2        | 1    | 0    | Rising (posedge)  | Falling (negedge) | ^M
*    | 3        | 1    | 1    | Falling (negedge) | Rising (posedge)  | ^M
*    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~          ^M
* ^M
*Note: conditional synthesis is done by using "generate if, end generate"     ^M
*************************************************************************/ ^M
/*simulation resolution*/ ^M