Honored Contributor
Honored Contributor--- quote start ---
mike you mean that the electrical layer is not the source of the problem ? it must be inside the fpga ? if so .. yes i agree with you.[/b]
--- quote end ---
in the fpga firmware is my guess.
<!--quotebegin-mschmitt@Aug 30 2005, 01:42 AM the first thing i will look after inside the uart core is, if the rxd signal is filtered. i would expect that the rxd signal is piped into a shift register where a 3 out of 4 detection triggers a srff. 3 one's will set and 3 zero's will clear this filtered rxd. if there is no filtering any glitch could trigger. --- Quote End --- I doubt that the Altera UART was designed to be bullet-proof at all. It looks like it's about as simple a UART implementation as possible. Simple edge checking for the start bit and one sample per data/parity/stop bit. This is more than enough for debug port and low-speed console applications. I think that Altera expected customers who needed more features to either buy a MegaCore (16450 or equivalent) or write their own.
