Honored Contributor
Honored ContributorHi slacker,
the uart delivers data that is definitly not part of the serial data stream. We have monitored the data that is transmitted from the uart to the nios with the signal tap by watching the readata and trigger set to chipselect with the adr equal to the databyte. Well as we do not have the source of this uart i agree that it could be that we see data that is beeing corrupted. we have no idea how we could see what is realy detected when the uart generates the receive interrupt. readdata is only valid during chipselect. and it could be that the time between generating the interrupt and accessing the data is too long but : we have a half dulpex transmission. the serial data stream is "idle" for a while, meaning continous 1 like stop bit the serial data stream starts with a 0x02 followed by some other data mostly the first data byte is received as 0x04 instead of 0x02 but the following bytes are mostly correct. so as 0x04 (the wrong data) is the first data being received and further data is correctly received by the same interrupt routine i don't think that the time between int generation and databyte access is the source. but maby somebody from altera can tell me what register inside the uart instead of readdata i should monitor with signaltap ... Regards Michael Schmitt BTW i have tried to re-open the mysupport request ...
