NIOS II Performance

Quartus tells you what FMax your design would run at with the setup you entered with these ip functionality you added.

As far as i had understand the Altera docs about the possible Fmax for a certain device or family. this FMax is possible but the more ip functionality or logic you add the lower FMax will be. Also it is not realy clear to me how this nios design is setup including everything to get these results. but is possible to reach the range Altera mentioned.

so you are right if Altera says 200 MHz is possible, but your quartus tells you 100MHz. So your fpga design under these conditions will not run safe with a higher frequency. of course there are some "tricks" you could do to speed up your design.

you could also be shure that the the fmax Altera mentiones is the highest possible for this device. if Altera does not know how to get more than your 230MHz who else would know ?

fmax depends on the timing you can reach with your design.

the timing depends on output settle time, logic equation time and some input timing (all inside your fpga f.e.)

now the logic between 2 Flip Flops must be fast enough that the summ of these 3 timings is less than 1/Fmax you desire. if the summ takes more time then the clock edge will clock your flip flop but the input is not ready, hope that helps to understand why you cann't increase your clock.