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It's all set up in the hardware through multi-mastering. In Qsys, connect all the cores to the on-chip memory. The base address for the memory for each core can be the same or unique for each one. It doesn't matter because each master has its own memory map. Then, in the BSP editor for each core, make sure the linker script is set up for the correct offset to the appropriate location in the memory.
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I guess you didn't get my point, I know what you are saying but the problem is 'To Access a Shared RAM' containing data like an array of 1024 elements which will be processed by four individual cores simultaneously. This 1024 elements array will be divided into four equal parts resulting in 256 elements for each core. This array is defined by the fifth core which is the master core and my question is 'How this master core inform the other four cores the address of this array, so that they can process their assigned 256 elements only and stop afterwards..
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