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You can have a fixed location in memory that you share between all your processors for message passing. You will also need a hardware mutex to ensure that two processors won't try to access it simultaneously. I think that Altera has a hardware mutex core designed for multiprocessor communication.
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You mean we can assign 'shared memory region' within the given On-chip memory?? If this is the case, then who will assign this region and how would other cores know about it?
And if we manage to do that, even then how master core inform other cores about the memory location of the declared array?
Simply, if there is an array of 1024 elements in the on-chip memory (shared), how each core will get to know about the starting and ending addresses of its part from those 1024 elements? hopefully you got the idea what I'm trying to say :-) Each core will process 256 elements in parallel with other cores so they should know where to find those 256 elements within the 1024 elements..
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