Nios II embedded multipliers

It's in the encrypted HDL that is generated for the Nios II core. You can see the number of multipliers up in the top left of the Quartus II screen where it shows you things like LEs, ALUTs, memory, etc... after a compilation. You might need to add multipliers to the view to see those. There should also be summaries of all the various blocks in the FPGA in the final compilation view for each level of hardware in your system.

On Stratix a single 32x32 multiplier should be used (1 cycle multiplication) and on Cyclone a 16x16 multiplier should be used (3 cycle multiplication). On Stratix this will be reported as a 36x36 multiplier block and on Cyclone this number will be reported as four 9x9 multiplier blocks (I think).