Nios II DDR SDRAM read latency

Hey dsl,

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I suspect your writes are repeatedly updating the same bytes in a 'pending line' register.

If you do random writes the 3rd and later probably have longer delays.

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The code is as follows:

// Write to RAM
	time1 = GET_TIMESTAMP;
	for (i = 0; i < 10000*5; i+=5)
	{
		IOWR(ALTMEMDDR_BASE, i, i);
		IOWR(ALTMEMDDR_BASE, i+1, i);
		IOWR(ALTMEMDDR_BASE, i+2, i);
		IOWR(ALTMEMDDR_BASE, i+3, i);
		IOWR(ALTMEMDDR_BASE, i+4, i);
	}
	time2 = GET_TIMESTAMP;
	printf("10'000 IOWR = %i\n", time2 - time1);
// Read from RAM
	time1 = GET_TIMESTAMP;
	for (i = 0; i < 10000*5; i+=5)
	{
		IORD(ALTMEMDDR_BASE, i);
		IORD(ALTMEMDDR_BASE, i+1);
		IORD(ALTMEMDDR_BASE, i+2);
		IORD(ALTMEMDDR_BASE, i+3);
		IORD(ALTMEMDDR_BASE, i+4);
	}
	time2 = GET_TIMESTAMP;
	printf("10'000 IORD = %i\n", time2 - time1);

Of course this is far from random. With true random access where columns and rows will change between each access, both read and write timing will increas significantly.

I just thought it is not fair to count the 4cc of the foor loop as IORD or IOWR time.

My goal is not to track down each and every clock cycle. I just wanted to get the overall picture.

In my real (unoptimized) project the situation is much worse. The following line takes about 300cc to execute:

memcpy(my_int, (alt_u8*)unaligned_address, 4);

This is owed to many factors:

- My data is not word-aligned in RAM, therefore memcopy does multiple individual reads.

- My Nios and RAM have different clock frequency, introducing slow clock-crossing bridges.

- My instruction code, as well as stack and heap are stored in RAM as well (same bank, different columns), so there are several reads just to get the instructions...

This is the reason I started looking at "what is the lowest latency for reading from SDRAM" at all :-P