Nios II DDR SDRAM read latency

If you are trying to time things, it is always worth looking at the generated code - just to check the compiler has generated the instruction sequence you think you are measuring.

I've measured the number of clocks for the nios cpu, the only undocumented stall I've seen is for a read of tightly coupled memory immediately following a write to the same memory block (the same probably applies for the data cache).

I suspect your writes are repeatedly updating the same bytes in a 'pending line' register.

If you do random writes the 3rd and later probably have longer delays.

I think that what you are seeing is a side effect of the access times of DRAM memory not really having improved very much (if at all). What has improved is the bandwidth for sequential access bursts.

Work out how many clocks a full DDR burst read takes - you might find it is much nearer to the clock count you are seeing.