Nios II CPU signals for signal tap 2

The "F_" is the fetch stage. Page 10 in this document shows all the stages for the Nios II 'f' core. As you can see the fetch stages is the first one.

If you are trying to follow what the CPU is executing you probably want to look at the execute stage ("E_") assuming synthesis doesn't rip it out. Otherwise just be aware that that the F_pcb is a few cycles ahead of what is actually being executed by the CPU.

Now if you simulated this you'll see copies of the program counter at every stage since you are looking directly at the HDL names instead of post synthesis names (most of which synthesis will rip out of your design). Typically I simulate my code running so that I can see all the program counter copies at the same time and see how the system is behaving around the processor.

I have never tried this myself but you might find this to be useful: http://www.altera.com/literature/an/an446.pdf