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Altera_Forum
Honored Contributor
14 years agoYou'd better read the TimeQuest tutorial for more comprehensive information. Anyway these are the minimal steps:
First of all check if the .sdc file generated by SOPC system is correctly included in project files. If not, add it (usually is cpu.sdc if you kept the default cpu name for Nios) Then create a new sdc file for your project (if not already done) and insert at least these commands: - create_clock for your input clock (if the input pin clock is clk50 it would be: create_clock -name {clk50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50}] - derive_pll_clocks - derive_clock_uncertainty Include also this file into the project and recompile. At the end, check if Quartus notifies any critical warning, about timing requirements not met. If you have them you can follow the hints from the timing optimization advisor (Tools menu). If you can't solve the problem immediately, further analysis with TQ is required in order to find out the failing paths.