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Altera_Forum
Honored Contributor
14 years agoNios II - Data cache problem
Hi all, I'm using a Cyclone III DSP Kit (DK-DSP-3C120N) and uClinux. Some days ago I realized a working design which includes a Nios II processor characterized by only an instruction cache. Wi...
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- The problem is due to data cache in Nios II processor because without it my software works :) I don't use ioremap_nocache. May I change something in my driver if I move from a processor with no data cache to a processor with data cache? --- Quote End --- You have to use ioremap_nocache to get a virtual address from your physical address. Then do all your access using that address. This will work with or without an MMU.