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Altera_Forum
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14 years ago

Nios II - Data cache problem

Hi all, I'm using a Cyclone III DSP Kit (DK-DSP-3C120N) and uClinux. Some days ago I realized a working design which includes a Nios II processor characterized by only an instruction cache. Wi...
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Altera_Forum
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14 years ago

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it seems that data do not leave the PIO.

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IIRC, the way to go is to define the MMU mapü in a way that the virtual address of the PIO is not cacheable.

-Michael