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Altera_Forum
Honored Contributor
14 years agoNios II - Data cache problem
Hi all, I'm using a Cyclone III DSP Kit (DK-DSP-3C120N) and uClinux. Some days ago I realized a working design which includes a Nios II processor characterized by only an instruction cache. Wi...
Altera_Forum
Honored Contributor
14 years agoYou'll need to do something to either flush the data from the cache, or to do uncached accesses.
uClinux ought to have functions to map the memeory uncached. You also need to ensure that you NEVER access any physical address in the same cache line via cachable accesses. The cache line read/write will have unwanted effects. For a hardware device this is unlikely, but can be a problem is you want a block of memory (eg for dma).