NIOS GPIO and Metastability question

Hi everyone!

Just a simple confirmation.

We had implemented an NIOS project with some GPIOs (the ones provided in QSYS)

The interfaces are asynchronous respect to the internal clock domain.

I assume initially that the input IPs for the NIOS had a double flipflop but looking at the RTL netlist I notice that there is combinatorial logic already at the input or after the first flip flop. :-/

So the NIOS GPIO is done basically for syncronous interfaces with the NIOS Clock and i case of asyncronous it is expect that the desinger manage the resampling for metastability outside?

Is my assumption correct?

thanks in advance

Ale