--- Quote Start ---
check epcs_flash_controller address and lock it to avoid any future modification. it must match EPCS_FLASH_CONTROLLER_0_BASE.
1024 bytes for the ROM is enough.
don't forget to initialize the ROM with "my_boot_loader_standalone.hex". Put this hex file in your project directory and point to it. (in sopc builder I write only "my_boot_loader_standalone" without any path or file extension in the "user created init file" field).
set the processor reset vector to this boot rom. "this boot rom" is 1024 bytes for the ROM that is initialize with "my_boot_loader_standalone.hex"?
"this boot rom" isn't epcs_flash.epcs_control_port? Reset vector isn't EPCS_FLASH_CONTROLLER_0_BASE?
I'm working this,but my system can't boot from EPCS. The Quartus is 13.0,Cyclon v 5CGXFC5C6,my Exception vector memory is DDR3.
Who can tell me this boot rom is what? on chip ram or epcs_flash.epcs_control_port? Reset vector is on chip ram' s address? or EPCS_FLASH_CONTROLLER_0_BASE?
Thank you!
--- Quote End ---
My software can works,but the hardware can't works. I set the processor reset vector to on_chip_ram that is 262144 Bytes. My exception vector memory is the same with rest vector memory in on_chip_ram.Is the on_chip_ram is too small to put hardware? The follow is my jic map file.
BLOCK START ADDRESS END ADDRESS
Page_0 0x00000000 0x001DE686
sw.hex 0x00800000 0x0081A37F
When I set exception vector memory is on DDR3. My software and hardware can't work. Why ? I test DDR3 with Run AS hardware,it is normally.
Thank you!
Honored Contributor
