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Altera_Forum
Honored Contributor
13 years agoThe design is using a watchdog timer, but it is handled the same way in any software versions. The only thing I modify is some delays and command given to others SOPC components.
The fpga configuration is the same on both hw, the only think that is changed is the time-stamp(multiple Regenerations and Recompilations, in lack of other ideas). For example: I have a hw(i won't modify it anymore) and sw version with a delay of 2s for a LED. If I put this on the flash, and reset the board by power off/on, the configuration runs. If I modify the delay with let's say 20s and RUN AS this new sw, the LED is powered on after 2s. If a put the sw version with 20s delay on flash and restart the board, it runs correctly. If I have another hw & sw versions stored on flash, and put the new hw with Quartus programmer, I may run successfully a new sw version on EVEN attempts.