Honored Contributor
Honored ContributorHi all,
After several debug tests, I think my problem is consecutive IRQ. Let me explain my current module : I have a module which consists of two FIFOs (FIFO 1 and FIFO 2). This module receives input data from outside (from a DSP Board). In the beginning the input data will enter the FIFO 1. After receiving a number of data, let say 1 frame, the module will generate an IRQ. Then, the CPU will handle the IRQ in the ISR, and the data from FIFO 1 are read. For the next frame data, it will be written in the FIFO 2. Then, again after completely receiving 1 frame data, the module will generate IRQ and the data from FIFO 2 are read. For the next frame data, the input data will be written again in the FIFO 1. So the writing process between FIFO 1 and FIFO 2 happen alternately. Since the IRQ is still generated from the same module, the IRQ either from FIFO1 or FIFO2 are handled by the same ISR. My problem now is when the ISR handles the IRQ from FIFO1, my IRQ signal keeps active. It seems the my program keep re-entering the ISR (so it likes consecutive IRQ). I've debugged my design & program and I can say that this situation is not caused by two interrupt that happens in the same time, because the writing duration for a FIFO is long enough. or in other words there is a long enough interval between two IRQ such that they don't overlap each other. So are there anyone who can help me to solve this consecutive IRQ problem ?? :( :( Thanks, I really appreciate any helps or suggestions.
