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Altera_Forum
Honored Contributor
15 years agoThe initial state will depend on the reset state of your logic.
So you need to clear it on sopc reset (and maybe from the nios soft reset). Having a separate software written 'interrupt enable' register may help here. I've not actually used the nios interrupt controller - so don't know if it has an IE mask, and have NFI what any altera startup code does! I don't have any external devices that are time-critical enough to require the cost of taking an interrupt. The code's idle loop checks the device registers directly (instead of looking at state set by an ISR). This avoids any need for disabling interrupts and cuts down on the number of cpu cycles needed to do the work (which is very critical for my code).